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features ? supply voltage up to 40v r dson typically 0.8 ? at 25c, maximum 1.8 ? at 200c up to 1.0a output current three half-bridge outputs formed by three high-side and three low-side drivers capable to switch all kinds of loads such as dc motors, bulbs, r esistors, capacitors and inductors no shoot-through current outputs short-circuit protected overtemperature protection for each switch and overtemperature prewarning undervoltage protection various diagnostic functions such as shorted output, open-load, overtemperature and power-supply fail detection serial data interface, daisy chain ca pable, up to 2 mhz clock frequency qfn18 package 1. description the ata6827 is a fully protected driver ic specially designed for high temperature applications. in mechatronic solutions, for example turbo charger or exhaust gas recir- culation systems, many flaps have to be c ontrolled by dc motor driver ics which are located very close to the hot engine or actuator where ambient temperatures up to 150c are usual. due to the advantages of soi technology junction temperatures up to 200c are allowed. this enables new co st effective board design possibilities to achieve complex mechatronic solutions. the ata6827 is a fully protected triple half-bridge to control up to 3 different loads by a microcontroller in automotive and industrial applications. each of the 3 high-side and 3 low-side drivers is capable to drive currents up to 1.0a. the drivers are internally connected to form 3 half-bridges and can be controlled separately from a standard serial data interface. therefore, all kinds of loads such as bulbs, resistors, capacitors and inductors can be combined. the ic des ign especially supports the application of h-bridges to drive dc motors. protection is guaranteed regarding short-ci rcuit conditions, overtemperature and und- ervoltage. various diagnostic functions and a very low quiescent current in standby mode opens a wide range of applications. automotive qualification gives added value and enhanced quality for exacting requirements of automotive applications. high temperature triple half-bridge driver with serial input control ata6827 preliminary 4912d?auto?06/07
2 4912d?auto?06/07 ata6827 figure 1-1. block diagram fault detector fault detector n. u. n. u. n. u. n. u. n. u. n. u. n. u. n. u. h s 2 l s 2 h s 1 l s 1 control logic 5 clk 7 do 8 inh 3 cs 4 di input register ouput register serial interface h s 3 l s 3 h s 2 l s 2 h s 1 l s 1 s r r h s 3 l s 3 o s c p s f fault detector n. u. n. u. n. u. t p n. u. n. u. n. u. o p l s c d fault detector fault detector power on reset charge pump uv protection thermal protection fault detector vs 10 vcc 9 gnd 6 gnd 18 gnd 17 gnd 14 out3f 1 out1f 15 out2f 12 vs 11 2 out3s 13 out2s 16 out1s
3 4912d?auto?06/07 ata6827 2. pin configuration figure 2-1. pinning qfn18 out3s out3f cs di clk gnd out2f vs vs vcc inh do pgnd3 pgnd1 out1s out1f pgnd2 out2s 1 2 3 4 5 6 12 11 10 9 8 7 18 17 16 15 13 14 table 2-1. pin description pin symbol function 1 out3s used only for final testing, to be connected to out3f 2 out3f half-bridge output 3 3 cs chip select input; 5-v cmos logic level input with internal pull up; low = serial communication is enabled, high = disabled 4 di serial data input; 5-v cmos logic level input with intern al pull down; receives serial data from the control device; di expects a 16-bit control word with lsb being transferred first 5 clk serial clock input; 5-v cmos logic level input with internal pull down; controls serial data input interface and internal shift register (f max = 2 mhz) 6 gnd ground; reference potential 7 do serial data output; 5-v cmos logic level tri-state out put for output (status) r egister data; sends 16-bit status information to the microcontroller (lsb is transferred first); output will remain tri-stated unless device is selected by cs = low, therefore, several ics can operate on one data output line only. 8 inh inhibit input; 5-v logic input with internal pull down; low = standby, high = normal operation 9 vcc logic supply voltage (5 v) 10 vs power supply for output stages out1, out2 and out3, internal supply 11 vs power supply for output stages out1, out2 and out3, internal supply 12 out2f half-bridge output 2 13 out2s used only for final testing, to be connected to out2f 14 pgnd2 power ground out2 15 out1f half-bridge output 1 16 out1s used only for final testing, to be connected to out13f 17 pgnd1 pgnd3 power ground out1 and out3 18 pgnd1 pgnd3 power ground out1 and out3
4 4912d?auto?06/07 ata6827 3. functional description 3.1 serial interface data transfer starts with the falling edge of th e cs signal. data must appear at di synchronized to clk and are accepted on the falling edge of the clk signal. lsb (bit 0, srr) has to be trans- ferred first. execution of new input data is enab led on the rising edge of the cs signal. when cs is high, pin do is in tri-state condition. th is output is enabled on the falling edge of cs. output data will change their state with th e rising edge of clk and stay st able until the next rising edge of clk appears. lsb (bit 0, tp) is transferred first. figure 3-1. data transfer srr ls1 hs1 ls2 hs2 ls3 hs3 n. u. n. u. n. u. n. u. n. u. n. u. ocs n. u. n. u. cs di clk do tp s1l s1h s2l s2h s3l s3h n. u. n. u. n. u. n. u. n. u. n. u. scd opl psf 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 table 3-1. input data protocol bit input register function 0srr status register reset (high = reset; the bits psf, opl and scd in the output data register are set to low) 1 ls1 controls output ls1 (high = switch output ls1 on) 2 hs1 controls output hs1 (high = switch output hs1 on) 3 ls2 see ls1 4 hs2 see hs1 5 ls3 see ls1 6 hs3 see hs1 7 n. u. not used 8 n. u. not used 9 n. u. not used 10 n. u. not used 11 n. u. not used 12 n. u. not used 13 ocs overcurrent shutdown (high = overcurrent shutdown is active) 14 n. u. not used 15 n. u. not used
5 4912d?auto?06/07 ata6827 table 3-2. output data protocol bit output (status) register function 0 tp temperature prewarning: high = warning 1 status ls1 high = output is on, low = output is off; not affected by srr 2 status hs1 high = output is on, low = output is off; not affected by srr 3 status ls2 description see ls1 4 status hs2 description see hs1 5 status ls3 description see ls1 6 status hs3 description see hs1 7 n. u. not used 8 n. u. not used 9 n. u. not used 10 n. u. not used 11 n. u. not used 12 n. u. not used 13 scd short circuit detected: set high when at least one high-side or low-side switch is switched off by a short-circuit condition. bits 1 to 6 can be used to detect the shorted switch. 14 opl open load detected: set high, when at least one active high-side or low-side switch sinks/sources a current below the open load threshold current. 15 psf power-supply fail: undervoltage at pin vs detected after power-on reset, the input register has the following status: bit 15 bit 14 bit 13 (ocs) bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 (hs3) bit 5 (ls3) bit 4 (hs2) bit 3 (ls2) bit 2 (hs1) bit 1 (ls1) bit 0 (srr) xxhxxxxxx lllllll the following patterns are used to enable internal test modes of the ic. it is not recommended to use these patterns during normal operation. bit 15 bit 14 bit 13 (ocs) bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 (hs3) bit 5 (ls3) bit 4 (hs2) bit 3 (ls2) bit 2 (hs1) bit 1 (ls1) bit 0 (srr) hhhhhlllllllllll hhhllhhlllllllll hhhllllhhlllllll
6 4912d?auto?06/07 ata6827 3.2 power-supply fail in case of undervoltage at pin vs, the power-supply fail bit (psf) in the output register is set and all outputs are disabled. to detect an undervoltage, its duration has to be longer than the undervoltage detection delay time t duv . the outputs are enabled immediately when supply volt- age recovers to a normal operating value. the psf bit stays high until it is reset by the srr (status register reset) bit in the input register. 3.3 open-load detection if the current through a high-side or low-side switch in the on-state stays below the open-load detection threshold, the open-load detection bit (opl) in the output register is set. the opl bit stays high until it is reset by the srr bit in the input register. to detect an open load, its duration has to be longer than the open-load detection delay time t dsd . 3.4 overtemperature protection if the junction temperature of one or more output stages exceeds the thermal prewarning thresh- old, t jpw set , the temperature prewarning bit (tp) in the output register is set. when the temperature falls below the t hermal prewarning threshold, t jpw reset , the bit tp is reset. the tp bit can be read without transferring a complete 16- bit data word. the status of tp is available at pin do with the falling edge of cs. after the microc ontroller has read this in formation, cs is set high and the data transfer is interrupted without affecting the status of input and output registers. if the junction temperature of one or more outp ut stages exceeds the thermal shutdown thresh- old, t j switch off , all outputs are disabled and the corresponding bits in the output register are set to low. the outputs can be enabled again when the temperature falls below the thermal shutdown threshold, t jswitch on and the srr bit in the input register is set to high. hysteresis of thermal pre- warning and shutdo wn threshold avoids oscillations. 3.5 short-circuit protection the output currents are limited by a current regulator. overcurrent detection is activated by writ- ing a high to the ocs (overcurrent shutdown) bit in the input register. when the current in an output stage exceeds the overcurrent limitation and shutdown threshold, it is switched off after a delay time (t dsd ). the short-circuit detection bit (scd) is set and the corresponding status bit in the output register is set to low. for ocs = low the overcurrent shutdown is inactive. the scd bit is also set if the current exceeds the overcurrent limitation and shutdown threshold, but the outputs are not affected. by writing a high to the srr bit in the input register the scd bit is reset and the disabled outputs are enabled. 3.6 inhibit applying 0v to pin 8 (inh) inhibits the ata6827. all output switches are then turned off and switched to tri-state. the data in the output register is deleted. the output switches can be activated again by switching pin 8 (inh) to 5v which ini- tiates an internal power-on reset.
7 4912d?auto?06/07 ata6827 4. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rati ng conditions for extended periods may affect device reliability . all values refer to gnd pins. parameters pin symbol value unit supply voltage 10, 11 v vs ?0.3 to +40 v supply voltage t < 0.5s; i s > ?2a 10, 11 v vs ?1 v logic supply voltage 9 v vcc ?0.3 to +7 v logic input voltage 3, 4, 5, 8 v cs ,v di , v clk , v inh ?0.3 to v vcc + 0.3 v logic output voltage 7 v do ?0.3 to v vcc + 0.3 v input current 3, 4, 5, 8 i cs , i di , i clk , i inh ?10 to +10 ma output current 7 i do ?10 to +10 ma output current 2, 12, 15 i out3 , i out2, i out1 internally limited, see output specification output voltage 2, 12, 15 i out3 , i out2, i out1 ?0.3 to +40 v reverse conducting current (t pulse =150 s) 2, 12, 15 i out3 , i out2, i out1 17 a junction temperature range t j ?40 to +200 c storage temperature range t stg ?55 to +200 c ambient temperature range t a ?40 to +150 c 5. thermal resistance parameters test conditions symbol value unit junction case r thjc maximum 15 k/w junction ambient (1) r thja 40 k/w notes: 1. depends on pcb board design 6. operating range parameters symbol value unit supply voltage v vs v uv (2) to 40 v logic supply voltage v vcc 4.75 to 5.25 v logic input voltage v cs ,v di , v clk , v inh ?0.3 to v vcc v serial interface clock frequency f clk 2 mhz junction temperature range t j ?40 to +200 c note: threshold for undervoltage detection
8 4912d?auto?06/07 ata6827 7. noise and surge immunity parameters test conditions value conducted interferences iso 7637-1 level 4 (1) interference suppression vde 0879 part 2 level 5 esd (human body model) esd s 5.1 2 kv cdm (charged device model) esd stm 5.3.1-1999 all pins 500v note: test pulse 5: v smax = 40v 8. electrical characteristics 7.5v < v vs < 40v; 4.75v < v vcc < 5.25 v; inh = high; ?40c t j 200 c; t a 150c; unless otherwise specified, all values refer to gnd pins. no. parameters test conditions pin symbol min. typ. max. unit type* 1 current consumption 1.1 quiescent current vs v vs < 20v, inh = low 10, 11 i vs 1 60 a a 1.2 quiescent current vcc 4.75 v < v vcc < 5.25v, inh = low 9 i vcc 15 40 a a 1.3 supply current vs v vs < 20v normal operating, all outputs off 10, 11 i vs 4 6 ma a 1.4 supply current vcc 4.75v < v vcc < 5.25v, normal operating 9 i vcc 350 500 a a 1.5 discharge current vs v vs = 32.5v, inh = low 10, 11 i vs 0.5 5.5 ma a 1.6 discharge current vs v vs = 40v, inh = low 10, 11 i vs 2.0 10 ma a 2 undervoltage detection, power-on reset 2.1 power-on reset threshold 9 v vcc 3.1 3.9 4.5 v a 2.2 power-on reset delay time after switching on v cc t dpor 30 95 190 s a 2.3 undervoltage-detection threshold v cc = 5v 10, 11 v uv 5.5 7.1 v a 2.4 undervoltage-detection hysteresis v cc = 5v 10, 11 ? v uv 0.6 v a 2.5 undervoltage-detection delay time t duv 10 40 s a 3 thermal prewarning and shutdown 3.1 thermal prewarning set t jpw set 170 195 220 c b 3.2 thermal prewarning reset t jpw reset 155 180 205 c b 3.3 thermal prewarning hysteresis ? t jpw 15 c b 3.4 thermal shutdown off t j switch off 200 225 250 c b 3.5 thermal shutdown on t j switch on 185 210 235 c b *) type means: a =100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. delay time between rising edge of the input signal at pi n cs after data transmission and s witch on output stages to 90% of final level. device not in standby for t > 1 ms
9 4912d?auto?06/07 ata6827 3.6 thermal shutdown hysteresis ? t j switch off 15 c b 3.7 ratio thermal shutdown off/thermal prewarning set t j switch off/ t jpw set 1.05 1.15 b 3.8 ratio thermal shutdown on/thermal prewarning reset t j switch on/ t jpw reset 1.05 1.15 b 4 output specificat ion (out1-out3) 4.1 on resistance i out 1-3 = ?0.9a 2, 12, 15 r dson1-3 1.8 ? a 4.2 i out 1-3 = +0.9a 2, 12, 15 r dson1-3 1.8 ? a 4.3 high-side output leakage current v out 1-3 = 0v , output stages off 2, 12, 15 i out1-3 ?60 a a 4.4 low-side output leakage current v out 1-3 = v vs, output stages off 2, 12, 15 i out1-3 300 a a 4.5 high-side switch reverse diode forward voltage i out 1-3 = 1.5a 2, 12, 15 v out1-3 ? v vs 2 v a 4.6 low-side switch reverse diode forward voltage i out 1-3 = ?1.5a 2, 12, 15 v out 1-3 ?2 v a 4.7 high-side overcurrent limitation and shutdown threshold 7.5v < v s < 20v 2, 12, 15 i out1-3 1.0 1.3 1.7 aa a 4.8 low-side overcurrent limitation and shutdown threshold 7.5v < v s < 20v 2, 12, 15 i out1-3 ?1.7 ?1.3 ?1.0 a a 4.18 high-side overcurrent limitation and shutdown threshold 20v < v s < 40v 2, 12, 15 i out1-3 1.0 1.3 2.0 aa a 4.19 low-side overcurrent limitation and shutdown threshold 20v < v s < 40v 2, 12, 15 i out1-3 ?2.0 ?1.3 ?1.0 a a 4.9 overcurrent shutdown delay time 2, 12, 15 t dsd 10 40 s a 4.10 high-side open-load detection threshold 2, 12, 15 i out1-3 ?55 ?30 ?5 ma a 4.11 low-side open-load detection threshold 2, 12, 15 i out1-3 5 30 55 ma a 4.12 open-load detection delay time t dsd 200 600 s a 8. electrical characteristics (continued) 7.5v < v vs < 40v; 4.75v < v vcc < 5.25 v; inh = high; ?40c t j 200 c; t a 150c; unless otherwise specified, all values refer to gnd pins. no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a =100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. delay time between rising edge of the input signal at pi n cs after data transmission and s witch on output stages to 90% of final level. device not in standby for t > 1 ms
10 4912d?auto?06/07 ata6827 4.13 high-side output switch on delay (1) v vs = 13v r load = 30 ? t don 20 s a 4.14 low-side output switch on delay (1) v vs = 13v r load = 30 ? t don 20 s a 4.15 high-side output switch off delay (1) v vs = 13v r load = 30 ? t doff 20 s a 4.16 low-side output switch off delay (1) v vs = 13v r load = 30 ? t doff 3sa 4.17 dead time between corresponding high- and low-side switches v vs = 13v r load = 30 ? t don ? t doff 1 s a 5 logic inputs di, clk, cs, inh 5.1 input voltage low-level threshold 3, 4, 5, 8 v il 0.3 v vcc v a 5.2 input voltage high-level threshold 3, 4, 5, 8 v ih 0.7 v vcc v a 5.3 hysteresis of input voltage 3, 4, 5, 8 ? v i 50 700 mv b 5.4 pull-down current pin di, clk, inh v di , v clk, v inh = v cc 4, 5, 8 i pd 5 70 a a 5.5 pull-up current pin cs v cs = 0v 3 i pu ?70 ?5 a a 6 serial interface ? logic output do 6.1 output-voltage low level i dol = 2 ma 7 v dol 0.4 v a 6.2 output-voltage high level i dol = ?2 ma 7 v doh v vcc ?0.7v v a 6.3 leakage current (tri-state) v cs = v cc 0v < v do < v vcc 7 i do ?15 +15 a a 7 inhibit input - timing 7.1 delay time from standby to normal operation t dinh 100 s a 8. electrical characteristics (continued) 7.5v < v vs < 40v; 4.75v < v vcc < 5.25 v; inh = high; ?40c t j 200 c; t a 150c; unless otherwise specified, all values refer to gnd pins. no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a =100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. delay time between rising edge of the input signal at pi n cs after data transmission and s witch on output stages to 90% of final level. device not in standby for t > 1 ms
11 4912d?auto?06/07 ata6827 9. serial interface ? timing no. parameters test conditions pin timing chart no. (1) symbol min. typ. max. unit type* 8.1 do enable after cs falling edge c do = 100 pf 7 1 t endo 200 ns d 8.2 do disable after cs rising edge c do = 100 pf 7 2 t disdo 200 ns d 8.3 do fall time c do = 100 pf 7 - t dof 100 ns d 8.4 do rise time c do = 100 pf 7 - t dor 100 ns d 8.5 do valid time c do = 100 pf 7 10 t doval 200 ns d 8.6 cs setup time 3 4 t cssethl 225 ns d 8.7 cs setup time 3 8 t cssetlh 225 ns d 8.8 cs high time 3 9 t csh 500 ns d 8.9 clk high time 5 5 t clkh 225 ns d 8.10 clk low time 5 6 t clkl 225 ns d 8.11 clk period time 5 - t clkp 500 ns d 8.12 clk setup time 5 7 t clksethl 225 ns d 8.13 clk setup time 5 3 t clksetlh 225 ns d 8.14 di setup time 4 11 t diset 40 ns d 8.15 di hold time 4 12 t dihold 40 ns d *) type means: a =100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. serial interface timing with chart numbers
12 4912d?auto?06/07 ata6827 figure 9-1. serial interface timing with chart numbers 1 do cs clk cs do clk output do: high level = 0.8 v cc , low level = 0.2 v cc inputs di, clk, cs: high level = 0.7 v cc , low level = 0.3 v cc di 11 5 6 8 10 12 3 9 2 4 7
13 4912d?auto?06/07 ata6827 10. application circuit figure 10-1. application circuit 11. application notes it is strongly recommended to connect the blocking capacitors at v cc and v s as close as possi- ble to the power supply and gnd pins. recommended value for capacitors at v s : electrolytic capacitor c > 22 f in parallel with a ceramic capacitor c = 100 nf. the value for electrolytic capacitor depends on external lo ads, conducted interferences and reverse conduct- ing current i out1,2,3 (see section 4. ?absolute maximum ratings? on page 7 ). recommended value for capacitors at v cc : electrolytic capacitor c > 10 f in parallel with a ceramic capacitor c = 100 nf. to reduce thermal resistance it is recommended to place cooling areas on the pcb as close as possible to the gnd pins and to the die pad. v cc v cc v cc + fault detector fault detector n. u. n. u. n. u. n. u. n. u. n. u. n. u. n. u. h s 2 l s 2 h s 1 l s 1 control logic 5 clk 7 do 8 inh u5021m watchdog enable reset trigger 3 cs 4 di input register ouput register serial interface h s 3 l s 3 h s 2 l s 2 h s 1 l s 1 s r r h s 3 l s 3 o s c p s f fault detector micro- controller n. u. n. u. n. u. t p n. u. n. u. n. u. o p l s c d fault detector fault detector power on reset charge pump uv protection thermal protection fault detector vs v s 13v v batt 5v v cc byt41d + 10 vcc 9 gnd 6 gnd 18 gnd 17 gnd 14 out3f 2 out1f 15 out2f m m 12 vs 11 1 13 16
14 4912d?auto?06/07 ata6827 13. package information 14. revision history 12. ordering information extended type number package remarks ATA6827-PIQW qfn18, 4 mm 4 mm taped and reeled, pb-free specifications according to din technical drawings 0.4 0.1 18 1 6 pin 1 identification 13 18 12 7 1 6 package: vqfn_4 x 4_18l exposed pad 2.7 x 3.175 dimensions in mm not indicated tolerances 0.05 issue: 1; 26.04.07 drawing-no.: 6.543-5133.01-4 0.2 2.5 0.175 0.5 nom. z 2.5 2.7 0.15 3.175 0.15 z 10:1 0.9 0.1 0.23 0.07 4 top bottom please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. revision no. history 4912d-auto-06/07 ? put datasheet in a new template ? package drawing changed ? block diagram changed ? pinning drawing changed ? pin description table changed ? application circuit drawing changed
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